VLSI (very large scale integration) design is making constant progress. Complexity is increasing and die sizes are decreasing. In parallel, costs are increasing and time-to-market requirements decrease at the same time. Therefore, it is a strong requirement to forward only working intermediate elements to a next production process. This applies also to ASICs (application specific integrated circuit). A key role in quality assurance of a production process for such ASICs take tests at every possible stage in order to avoid continuation with a non-working part in a subsequent production step. During the manufacturing process, electronic circuit testing generally occurs at many levels of integration of the circuit via various testing techniques. Generally, testing may occur at wafer level, package level, multi-chip module level, board level, and system level. Wafer level testing may happen during early stages of a production process, namely before a singularization, i.e., before the chips or dies may be separated from each other and the remaining parts of a wafer.
A goal of testing at each level is to detect as many defect circuits as possible as early as possible in the production process. Passing a defect circuit to a next production phase may increase the overall production costs. The later a defect may be detected, the higher the overall costs may be. Therefore, manufacturers of such devices are strongly interested to decrease the number of defect parts as early as possible in the production process.
At wafer level, the testing goal may be to separate good dies from bad ones before sawing and component packaging. However, it may be understood that a complete functional test may only be possible at board and/or system level, i.e., if all supporting mechanical, electrical, and electronic elements are assembled in a final product. In production phases or levels thereof, only substitute tests may be performed. That may include parametric testing, including current monitoring testing at wafer level and/or built-in self tests. These so-called BISTs at wafer level may use automated hardware-based tests included inside the tested chip which may allow the circuit to test itself. A BIST may occur online during normal operation of the chip during an idle state or offline when the circuit may be placed in a special test mode. During wafer level testing, online BIST may be employed and may generally include a hardware pseudo-random vector generator and signature analysis hardware. Although the BIST techniques may be an effective method of detecting so-called “stuck-at” and delay type faults, it may require costly testing time and die space for a required ROM (read-only memory). Additionally, in a ROM-based BIST, the micro-program-based functional test may be developed and frozen by R&D in the design stage before a product may be ramped to production. Thus, the ROM-based BIST is static and alterations may not be possible at all.
Several attempts have been made in order to better test ASICs and other VLSI chips. Document U.S. Pat. No. 5,937,154 discloses a manufacturing test system and method for testing a computing system under test, which includes a computing device comprising internal emulation debug hardware, and an emulation debug port through which the debug hardware is controlled. Manufacturing-level micro-program based functional tests are executed under the control of the internal emulation debug hardware of the computing device. A computing system probe applies the micro-program-based functional test to the internal emulation debug hardware of the computing device via the emulation debug port. The manufacturing-level micro-program-based functional test may be executed at any level of a computing device integration including the wafer, package, board, multi-chip module and system levels.
Document U.S. Pat. No. 6,825,682B2 discloses a test configuration for the functional testing of a semiconductor chip. The semiconductor chip, which can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip, is disposed on a support material. The semiconductor chip contains a self-test unit for generating test information and for carrying out the functional test. An energy source serves for providing an electrical energy supply for energy that is fed-in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for the purpose of providing an energy supply. The test configuration makes it possible to carry out a contactless functional test and to reduce the test costs by virtue of high parallelism during the functional test of a plurality of semiconductor chips.
It may also be understood that due to the complexity of today's VLSI ASICs, a complete test of all statuses and functions may not be feasible. This may apply in particular, if the VLSI ASIC may include a complete processor, memory and other supporting devices. It may become even more difficult if the processor's functionality may be altered by using different microcode sets. The term microcode may denote a set of instructions that may be stored inside the processor during an initialization phase. It may determine the function of the processor and its behavior in respect to external/conventional program code and data. Thus, different microcode sets may result in a different behavior of a processor to the same external/conventional program code and data. In such a scenario, a complete test of all possible microcode sets in combination with all possible external program code and data may not be feasible. Even a small subset of combinations would lead to an explosion of production cost. It may be noted that instead of the term “microcode” the term “firmware” may also be used. Also the term “micro-program” may be a substitute for the term “microcode”.
However, because of the limitations of the technology of the state of the art, there may be a requirement for an improved method and system for a better testability of VLSI chips that may not rely on built-in-self-tests or random signal generators. These test measures may be too late or to imprecise.